Low-Voltage Differential Signaling (LVDS) is an interface standard that can be used for high-speed data transmission. By using low swing signals (typically about 300 mV), faster bit rates, lower power, and better noise performance can be achieved. The differential nature of signals generally allows for increased noise immunity and noise margins. Examples of applications that use LVDS signaling include hubs for data communications, base stations and switches for telecommunications, flat-panel displays, servers, peripheral devices (e.g., printers and digital copy machines), and high-resolution displays for industrial applications.
A conventional LVDS input circuit 100 is shown in FIG. 1. The LVDS input circuit 100 is commonly referred to as a LVDS receiver as well. The LVDS input circuit 100 includes two input pads 101 and 103, three n-type metal oxide semiconductor (NMOS) (i.e., n-channel) transistors Q1, Q2, and Q3, a termination resistor R1, and two pull-up resistors R2 and R3. The termination resistor R1 is coupled in between the two input pads 101 and 103. The LVDS input signals, lvds_in_p and lvds_in_n, are applied to the gates of the transistors Q1 and Q2 via the input pads 101 and 103, respectively. The transistors Q1 and Q2 form a differential gate. The transistor Q3 is biased by a predetermined voltage, nbias, to provide a current sink to the transistors Q1 and Q2. The pull-up resistors R2 and R3 couple the transistors Q1 and Q2, respectively, to a voltage supply, vddio 109. The output signals of the receiver circuit 100 are dfl_out_n and dfl_out_p at the drains of the transistors Q1 and Q2, respectively.
However, the above LVDS input circuit 100 is unsatisfactory because of several disadvantages. One disadvantage is the severely limited common mode range of the LVDS input circuit 100. The upper limit of the common mode range is limited by the power supply voltage (i.e., vddio 109 in FIG. 1). So, a 2.5V supply voltage is provided for a 2.5V common mode voltage. Furthermore, the lower limit of the common mode range is determined by the threshold voltage (Vt) of the NMOS transistors (Q1 and Q2) and the drain-to-source (Vds) voltage of the transistor Q3 of the current sink. As a result, the common mode range of the LVDS input circuit 100 is typically limited to a lower limit of at least about 0.8V.